ARCHITECTURE AND PROGRAMMING OF SCALABLE COMPUTERS WITH HIGH PERFORMANCE AND LOW CONSUMPTION (Q3141964): Difference between revisions
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(Created claim: summary (P836): THE INCREASED INTEGRATION CAPACITY ALLOWS THE NUMBER OF PROCESSORS AND THE SIZE OF THE ON-CHIP MEMORY TO CONTINUE TO GROW. THERE ARE MORE AND MORE RESOURCES, AND NOT ONLY IN THE CALCULATION SERVERS, BUT ALSO IN THE SOCS FOR EMBEDDED AND PORTABLE DEVICES. THERE IS ALSO A CLEAR TREND TOWARDS HETEROGENEOUS SYSTEMS. A MAJOR CURRENT CHALLENGE IN COMPUTER ARCHITECTURE IS TO LEVERAGE THIS GROWING AMOUNT OF RESOURCES EFFICIENTLY, PAYING ATTENTION TO BOT...) |
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ARCHITECTURE AND PROGRAMMING OF SCALABLE COMPUTERS WITH HIGH PERFORMANCE AND LOW CONSUMPTION | |||
Revision as of 13:25, 12 October 2021
Project Q3141964 in Spain
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | ARCHITECTURE AND PROGRAMMING OF SCALABLE COMPUTERS WITH HIGH PERFORMANCE AND LOW CONSUMPTION |
Project Q3141964 in Spain |
Statements
109,868.0 Euro
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219,736.0 Euro
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50.0 percent
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30 December 2016
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31 December 2020
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UNIVERSIDAD DE ZARAGOZA
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41°39'7.67"N, 0°52'51.38"W
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50297
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EL INCREMENTO DE LA CAPACIDAD DE INTEGRACION PERMITE QUE EL NUMERO DE PROCESADORES Y EL TAMAÑO DE LA MEMORIA ON-CHIP CONTINUE CRECIENDO. CADA VEZ HAY MAS RECURSOS, Y NO SOLO EN LOS SERVIDORES DE CALCULO, SINO TAMBIEN EN LOS SOCS PARA DISPOSITIVOS EMPOTRADOS Y PORTATILES. EXISTE ADEMAS UNA CLARA TENDENCIA HACIA LOS SISTEMAS HETEROGENEOS. UN IMPORTANTE RETO ACTUAL EN ARQUITECTURA DE COMPUTADORES ES APROVECHAR ESTA CRECIENTE CANTIDAD DE RECURSOS DE FORMA EFICIENTE, ATENDIENDO TANTO AL RENDIMIENTO COMO AL CONSUMO ENERGETICO. JUNTO CON EL FRENO DEL PARALELISMO DE INSTRUCCION DEL PROCESADOR, EL AUMENTO DEL PARALELISMO DE COMPONENTES REALZA CADA VEZ MAS EL PAPEL DE LAS REDES DE INTERCONEXION Y LA JERARQUIA DE MEMORIA, QUE DESEMPEÑAN PAPELES CADA VEZ MAS CRITICOS EN LA INGENIERIA DE TODO TIPO DE COMPUTADORES._x000D_ EL PRIMER RETO ES ANALIZAR LAS POSIBILIDADES DE DISEÑO, TANTO DE LA RED DE INTERCONEXION COMO DE LA JERARQUIA DE MEMORIA, PARA IDENTIFICAR SOLUCIONES QUE PERMITAN CONSTRUIR SISTEMAS EN CHIP MASIVAMENTE PARALELOS Y EFICIENTES. PARA ELLO SE ESTUDIARA LA ESCALABILIDAD DE DISTINTAS ALTERNATIVAS DE REDES EN CHIP Y SE DISEÑARAN SOLUCIONES QUE REDUZCAN SU CONSUMO. TAMBIEN SE PROPONDRAN MECANISMOS QUE PERMITAN MEJORAR EL RENDIMIENTO Y AHORRAR AREA Y ENERGIA EN LA JERARQUIA DE MEMORIA, TANTO EN MULTIPROCESADORES COMO EN SISTEMAS HETEROGENEOS. INEVITABLEMENTE, EL ESTUDIO DE COMPUTADORES QUE UTILIZAN MULTIPLES CHIPS NOS LLEVA A LAS REDES DE SISTEMA. EN ESTE DOMINIO SE PROPONDRAN NUEVAS TOPOLOGIAS DE BAJO DIAMETRO Y DISTANCIA MEDIA, PARA HPC Y DATA CENTERS, ASI COMO NUEVOS MECANISMOS DE EVITACION DE DEADLOCK Y OTROS ASPECTOS DE LA ARQUITECTURA INTERNA DE LOS ROUTERS QUE MEJOREN SU RENDIMIENTO Y CONSUMO._x000D_ EN UN SEGUNDO RETO ABORDAREMOS LA GESTION DE LOS RECURSOS DISPONIBLES EN ENTORNOS DE TIEMPO REAL EN LOS QUE SE DEBE GARANTIZAR EL CUMPLIMIENTO DE RESTRICCIONES TEMPORALES. EXPLORAREMOS DISTINTAS TECNICAS DE CALCULO DEL TIEMPO DE EJECUCION EN EL PEOR CASO (WCET) -QUE TIPICAMENTE SE APLICAN A PROGRAMAS PEQUEÑOS- PARA APLICACIONES GRANDES, DESARROLLANDO LAS METODOLOGIAS NECESARIAS. TAMBIEN CARACTERIZAREMOS LAS REFERENCIAS A DATOS Y DISEÑAREMOS HARDWARE ESPECIFICO PARA MEJORAR EL RENDIMIENTO DE LOS SISTEMAS DE TIEMPO REAL EN EL PEOR CASO._x000D_ EL TERCER RETO CONSISTE EN DESARROLLAR UNA SERIE DE ALGORITMOS Y HERRAMIENTAS QUE PERMITAN SIMPLIFICAR LA PROGRAMACION DE APLICACIONES OPENCL QUE SEAN EXTREMADAMENTE PORTABLES, TANTO EN CODIGO, COMO EN RELACION A SU RENDIMIENTO Y CONSUMO ENERGETICO. SE PROPONDRAN SOLUCIONES QUE PERMITAN OPTIMIZAR RENDIMIENTO Y CONSUMO ENERGETICO O BIEN OBTENER UN EQUILIBRIO ENTRE AMBOS. ADEMAS, SE TENDRAN EN CUENTA LAS RESTRICCIONES TERMICAS EN TIEMPO REAL, DESARROLLANDO PLANIFICADORES QUE EVITEN LA FORMACION DE PUNTOS CALIENTES Y EVITEN FALLOS TEMPRANOS O ENVEJECIMIENTO PREMATURO._x000D_ EL ULTIMO RETO DE ESTE PROYECTO ES DISEÑAR Y ACELERAR LA EJECUCION DE APLICACIONES APROVECHANDO NUESTRO CONOCIMIENTO DE LA INTERACCION HARDWARE/SOFTWARE. ESTE TRABAJO SE APLICARA TANTO A ENTORNOS DE ALTO RENDIMIENTO COMO A SOLUCIONES A MEDIDA PARA DISPOSITIVOS MOVILES, EN LOS QUE LA EFICIENCIA ENERGETICA ES UNA PRIORIDAD. SE PROPONDRAN SOLUCIONES QUE DESARROLLEN ALGORITMOS MAS EFICIENTES PARA UNA ARQUITECTURA DADA, Y SOLUCIONES QUE USEN ACELERADORES HARDWARE A MEDIDA. LAS APLICACIONES OBJETIVO TIENEN GRAN RELEVANCIA CIENTIFICA Y SOCIAL, COMO APLICACIONES DE IMAGENES HIPERESPECTRALES, INTELIGENCIA ARTIFICIAL O DINAMICA MOLECULAR. (Spanish)
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THE INCREASED INTEGRATION CAPACITY ALLOWS THE NUMBER OF PROCESSORS AND THE SIZE OF THE ON-CHIP MEMORY TO CONTINUE TO GROW. THERE ARE MORE AND MORE RESOURCES, AND NOT ONLY IN THE CALCULATION SERVERS, BUT ALSO IN THE SOCS FOR EMBEDDED AND PORTABLE DEVICES. THERE IS ALSO A CLEAR TREND TOWARDS HETEROGENEOUS SYSTEMS. A MAJOR CURRENT CHALLENGE IN COMPUTER ARCHITECTURE IS TO LEVERAGE THIS GROWING AMOUNT OF RESOURCES EFFICIENTLY, PAYING ATTENTION TO BOTH PERFORMANCE AND ENERGY CONSUMPTION. Together with the paralysing parallelism of the processor, the increase of the parallelism of compounds excels EVERY more than the paddle of the interconnecting nets and the MEMORIA JERARQUIA, who desempeÑAN PAPELES EVERY HIGH CRITICAL IN THE INGENIERIA OF ALL COMPUTATOR TYPES._x000D_ The first challenge is to analyse the handicappednesses, as of the interconnecting network as of the MEMORIA JERARQUIA, for identification of solutions that allow to build systems in most paralysed and effective CHIP. TO THIS END, THE SCALABILITY OF DIFFERENT ALTERNATIVES OF CHIP NETWORKS WILL BE STUDIED AND SOLUTIONS DESIGNED TO REDUCE THEIR CONSUMPTION. MECHANISMS WILL ALSO BE PROPOSED TO IMPROVE PERFORMANCE AND SAVE AREA AND ENERGY IN THE HIERARCHY OF MEMORY, BOTH IN MULTIPROCESSORS AND IN HETEROGENOUS SYSTEMS. INEVITABLY, THE STUDY OF COMPUTERS THAT USE MULTIPLE CHIPS LEADS US TO SYSTEM NETWORKS. New DIAMETER and MEDIA DISTANCY TOPOLOGIAS, for HPC and DATA CENTERS, as well as new DEADLOCK-avoidance mechanisms and other aspectories of the internal architecture of the ROUTERS who improve their income and consumption._x000D_ will be proposed in this domain. we challenge the management of available resources in real time environments in which the accounting of time constraints should be guaranteed. WE WILL EXPLORE DIFFERENT TECHNIQUES OF CALCULATING THE EXECUTION TIME IN THE WORST CASE (WCET) — WHICH TYPICALLY APPLY TO SMALL PROGRAMS — FOR LARGE APPLICATIONS, DEVELOPING THE NECESSARY METHODS. We will also characterise DATA REFERENCES and design HARDWARE SPECIFIC to improve the return of real-time systems in the worst case._x000D_ THE THIRD REPORTS CONSISTS IN DEVELOPING A SERIE OF ALGORITMS AND TOOLS PERMITING THE PROGRAMME OF OPENCLAL APPLICATIONS THAT IS EXTREMELY PORTABLE, as in relation to your surrender and ENERGETIC consummation. SOLUTIONS WILL BE PROPOSED TO OPTIMISE PERFORMANCE AND ENERGY CONSUMPTION OR TO ACHIEVE A BALANCE BETWEEN THE TWO. In addition, take into account thermal hazards in real time, development of palliative development that prevents the formation of hotheads and avoids temporary or ageing fades._x000D_ The challenge of this project is to be designed and implemented application PROVIDEDING OUR KNOWING OF THE HARDWARE/SOFTWARE INTERACTION. THIS WORK WILL BE APPLIED TO BOTH HIGH PERFORMANCE ENVIRONMENTS AND CUSTOM SOLUTIONS FOR MOBILE DEVICES, WHERE ENERGY EFFICIENCY IS A PRIORITY. SOLUTIONS WILL BE PROPOSED THAT DEVELOP MORE EFFICIENT ALGORITHMS FOR A GIVEN ARCHITECTURE, AND SOLUTIONS THAT USE CUSTOM HARDWARE ACCELERATORS. THE TARGET APPLICATIONS HAVE GREAT SCIENTIFIC AND SOCIAL RELEVANCE, SUCH AS APPLICATIONS OF HYPERSPECTRAL IMAGES, ARTIFICIAL INTELLIGENCE OR MOLECULAR DYNAMICS. (English)
12 October 2021
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Zaragoza
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Identifiers
TIN2016-76635-C2-1-R
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